Xilinx Virtex-5 FPGA ML561 - Manual (Page 61)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 61
UG199 (v1.2.1) June 15, 2009
Signal Integrity Correlation Results R
Figure 7-4: DDR2 Component Write HW Measurement - Eye Scope Shot at Probe Point (DDR2 Memory Via)
UG199_c7_04_071107
Figure 7-5: DDR2 Component Write Correlation - Eye Scope Shot at Probe Point (Slow Corner)
0.000 400.0 800.0 1200.0 1600.0
-200.0
0.000
200.0
400.0
600.0
800.0
1000.0
Voltage (mV)
1200.0
1400.0
1600.0
1800.0
Time (ps)
Probe 3:C9.1 (at pin)
UG199_c7_05_070907
♦
333 MHz, Slow, PRBS6, 81.5% UI
♦
Cursor 1: 1.1028V, 123.6 ps
♦
Cursor 2: 1.0253V, 1.3458 ns
♦
Delta Voltage = 77.5 mV, Delta Time = 1.2222 ns (81.5% UI)