Xilinx Virtex-5 FPGA ML561 - Manual (Page 126)

126 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix C: LCD Interface R
Controller – Power Supply Circuits
Figure C-5 shows the power supply circuits. The power supply is used in the five times
boost mode, where VDD is 3.3V and VOUT is 16.5V. VOUT is the operating voltage of the
operational amplifier delivering the operating voltage, V0, for the LCD panel.
The LCD operating voltage, V0, is set with two resistors R
A
and R
B
. INTRS is driven Low
when the resistors are external. INTRS is driven High when the resistors are internal. For
the Virtex-5 FPGA ML561 Development Board, internal resistors are selected.
The LCD operating voltage (V0) and the Electronic Volume Voltage (V
EV
) can be calculated
in units of V using Equation C-1 and Equation C-2 :
Equation C-1
Equation C-2
In Equation C-2 , V
REF
is equal to 2.0V at 25 °C.
The values of the reference voltage parameter, α, and the ratio R
A
/R
B
are determined with
bit settings in the LCD controller’s instruction registers. Thus, it is possible to change
physical operating parameters of the LCD through register bit settings, controlling the
operating voltage, and the electronic volume level.
Figure C-5: Power Supply Circuits
DUTY1
DUTY2
BSTS
VR
MS
INTRS
17 VDD
18 VOUT
25
26
27
28
29
30 VSS1
2
1
VDD
VSS
VOUT
5 x VDD
VDD
VSS
16 VSS
DCDC5B
UG199_C_05_050106
V0 1
R
B
R
A
------- +
⎝ ⎠
⎛ ⎞
V
EV
×
=
V
EV
1
63
α
–
300
--------------- –
⎝ ⎠
⎛ ⎞
V
REF
Ч
=