Xilinx Virtex-5 FPGA ML561 - Manual (Page 25)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 25
UG199 (v1.2.1) June 15, 2009
Memory Details R
QDRII and RLDRAM II Memories
Figure 3-5 summarizes the distribution of QDRII and RLDRAM II component interface
signals among the different banks of the FPGA #3 device.
Figure 3-5: FPGA #3 Banks for QDRII SRAM and RLDRAM II Interfaces (Top View)
BANK 20 (40)
RLDII Data
DQ 0, 1 & D0
BANK 12 (40)
RLDII Data
DQ 2, 3 & D1
BANK 11 (40)
QDRII Data
Q0, 2 & D6
BANK 112
BANK 114 BANK 13 (40)
QDRII Data
Q4, 5, 6
BANK 15 (40)
QDRII Data
D7, 2, 3, 0
BANK 116
BANK 19 (40)
QDRII Data
Q1, 3 & D1
BANK 120
(Configuration)
BANK 0
BANK 3 (20)
General I/O
BANK 5 (20) BANK 23 (40) BANK 124
BANK 1 (20)
System ACE Controls
BANK 18 (40)
RLDII Data
D 2, 3
BANK 17 (40)
QDRII Data
Q7 & D4, 5
BANK 118
BANK 22 (40)
RLDII Address
and Control
BANK 122 BANK 21 (40)
QDRII Address
and Control
BANK 2 (20)
Inter-FPGA MII Links
BANK 25 (40) BANK 126 BANK 6 (20)
BANK 4 (20)
Global Clock Inputs
UG199_c3_05_050106