Xilinx Virtex-5 FPGA ML561 - Manual (Page 65)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 65
UG199 (v1.2.1) June 15, 2009
Signal Integrity Correlation Results R
DDR2 Component Read Operation
This subsection shows the test results for the DDR2_DQ_BY2_B3 signal from the DDR2
memory component (U12) to FPGA1 (U7) measured at 333 MHz (667 Mb/s), where the
unit interval (UI) = 1.5 ns.
To perform hardware measurements for a Read operation that is not interrupted by a Write
or a Refresh operation, the testbench on FPGA1 is controlled by the following DIP switch
(SW2) setting:
•
DIP[1:2] = 2’b10 – Write once, then Read only, Refresh disabled
Figure 7-12: Post-Layout IBIS Schematics of the DDR2 Component Read Data Bit (DDR2_DQ_BY2_B3)
49.0 ohms
24.721 ps
0.164 in
DDR2_DQ_BY2_B3 28.5 ohms
3.579 ps
0.022 in
DDR2_DQ_BY2_B3
MT47H64M8CB-3
DQ3
TL2 TL3 TL4 TL8 TL9 TL6 TL5 TL1 U7.P25
C7 C9
U12.D3
49.1 ohms
47.132 ps
0.302 in
DDR2_DQ_BY2_B3 58.3 ohms
25.244 ps
AutoPadstk_19 21.2 ohms
1.000 ps
AutoPadstk_3 71.0 ohms
27.482 ps
AutoPadstk_3 49.1 ohms
445.560 ps
2.852 in
DDR2_DQ_BY2_B3 28.5 ohms
4.473 ps
0.028 in
DDR2_DQ_BY2_B3
Virtex-5 FPGA
DDR2_DQ_BY2_B3
22.9 fF 22.9 fF 500.0 fF
58.1 fF 140.8 fF
DDR2_D…
DDR2_D… DDR2_D…
DDR2_D…
DDR2_D… DDR2_D…
365.6 fF 500.0 fF
22.9 fF
UG199_c7_12_071907
Table 7-4: Circuit Elements of DDR2 Component Read Data Bit
(DDR2_DQ_BY2_B3)
Element Designation Description
Driver U12.D3 DDR2 Memory
Receiver U7.P25 FPGA SSTL18_II_DCI_I
Probe Point C7 Via under FPGA1
PCB Termination None DCI at receiver
Trace Length TL 2, 4, 9, 6, 1 3.37 inches
Table 7-5: DDR2 Component Read Operation Correlation Results
Measurement DVW (% UI)
ISI
(% UI)
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot /
Undershoot Margin
(% of VREF)
Hardware at probe point
1.28 ns
(85%)
(70 + 110) = 180 ps
(12%)
(423 + 416) = 839 mV
(83.1%)
(400 +400) = 800 mV
(79.1%)
Simulation correlation
slow-weak corner 1.28 ns
(85%)
(132 + 91) = 223 ps
(14.9%)
(406 +439) = 845 mV
(83.8%)
(279 +277) = 556 mV
(61.9%)
Correlation Delta:
HW vs. Simulation 0 ps
(0.0%)
43 ps
(2.9%)
6 mV
(0.7%)
244 mV
(17.2%)
Extrapolation at IOB
slow-weak corner 1.29 ns
(86%)
(96 + 82) = 178 ps
(11.9%)
(418 + 449) = 867 mV
(96.3%)
(304 +265) = 569 mV
(63.1%)
Extrapolation at IOB
fast-strong corner 1.32 ns
(88%)
(29 + 67) = 96 ps
(6.7%)
(455 +435) = 890 mV
(98.9%)
(167 +182) = 349 mV
(38.9%)