Xilinx Virtex-5 FPGA ML561 - Manual (Page 2)

Virtex-5 FPGA ML561 User Guide www.xilinx.com UG199 (v1.2.1) June 15, 2009
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Revision History
The following table shows the revision history for this document.
Date Version Revision
02/12/07 1.0 Initial Xilinx release.
08/09/07 1.1 Revised Read and Write Strobe in Table 5-4, page 49 . Added Chapter 7, “ML561
Hardware-Simulation Correlation.”
04/19/08 1.2 Revised Figure 3-11, page 37 and Table 3-19, page 38 . Corrected FPGA driver for Read
Data and Read Strobe in Table 5-4, page 49 . Updated Data and Strobe entries in Table 5-5,
page 49 . Updated manufacturers and links in Appendix B, “Bill of Materials.”
06/15/09 1.2.1 Clarified VIH(max) voltage in “Terminology.”
R