Xilinx Virtex-5 FPGA ML561 - Manual (Page 101)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 101
UG199 (v1.2.1) June 15, 2009
FPGA #2 Pinout R
DDR2 DIMM Deep Interface (cont.)
DDR2_DIMM3_CK2_P AA25 DDR2_DIMM_DQ_BY0_B4 R27
DDR2_DIMM3_CKE0 AE28 DDR2_DIMM_DQ_BY0_B5 R26
DDR2_DIMM3_CKE1 AH28 DDR2_DIMM_DQ_BY0_B6 U28
DDR2_DIMM3_CS0_N W25 DDR2_DIMM_DQ_BY0_B7 U27
DDR2_DIMM3_CS1_N V25 DDR2_DIMM_DQ_BY1_B0 N29
DDR2_DIMM3_ODT0 AB26 DDR2_DIMM_DQ_BY1_B1 M30
DDR2_DIMM3_ODT1 AB25 DDR2_DIMM_DQ_BY1_B2 L30
DDR2_DIMM4_CK0_N AK9 DDR2_DIMM_DQ_BY1_B3 J31
DDR2_DIMM4_CK0_P AK8 DDR2_DIMM_DQ_BY1_B4 J30
DDR2_DIMM4_CK1_N AJ11 DDR2_DIMM_DQ_BY1_B5 G31
DDR2_DIMM4_CK1_P AK11 DDR2_DIMM_DQ_BY1_B6 H30
DDR2_DIMM4_CK2_N AD11 DDR2_DIMM_DQ_BY1_B7 L29
DDR2_DIMM4_CK2_P AD10 DDR2_DIMM_DQ_BY2_B0 E31
DDR2_DIMM4_CKE0 AG11 DDR2_DIMM_DQ_BY2_B1 F31
DDR2_DIMM4_CKE1 AG10 DDR2_DIMM_DQ_BY2_B2 J29
DDR2_DIMM4_CS0_N W26 DDR2_DIMM_DQ_BY2_B3 H29
DDR2_DIMM4_CS1_N Y26 DDR2_DIMM_DQ_BY2_B4 F30
DDR2_DIMM4_ODT0 AE11 DDR2_DIMM_DQ_BY2_B5 G30
DDR2_DIMM4_ODT1 AF11 DDR2_DIMM_DQ_BY2_B6 F29
DDR2_DIMM_DM_BY0 U30 DDR2_DIMM_DQ_BY2_B7 E29
DDR2_DIMM_DM_BY1 R31 DDR2_DIMM_DQ_BY3_B0 J32
DDR2_DIMM_DM_BY2 T31 DDR2_DIMM_DQ_BY3_B1 F34
DDR2_DIMM_DM_BY3 L33 DDR2_DIMM_DQ_BY3_B2 G33
DDR2_DIMM_DM_BY4 AK34 DDR2_DIMM_DQ_BY3_B3 E33
DDR2_DIMM_DM_BY5 AG32 DDR2_DIMM_DQ_BY3_B4 E32
DDR2_DIMM_DM_BY6 P34 DDR2_DIMM_DQ_BY3_B5 E34
DDR2_DIMM_DM_BY7 AK33 DDR2_DIMM_DQ_BY3_B6 F33
DDR2_DIMM_DM_CB0_7 M32 DDR2_DIMM_DQ_BY3_B7 G32
DDR2_DIMM_DQ_BY0_B0 T25 DDR2_DIMM_DQ_BY4_B0 Y34
DDR2_DIMM_DQ_BY0_B1 U25 DDR2_DIMM_DQ_BY4_B1 AA34
DDR2_DIMM_DQ_BY0_B2 T26 DDR2_DIMM_DQ_BY4_B2 AA33
DDR2_DIMM_DQ_BY0_B3 U26 DDR2_DIMM_DQ_BY4_B3 Y33
Table A-2: FPGA #2 Pinout (Continued)
Signal Name Pin Signal Name Pin