Xilinx Virtex-5 FPGA ML561 - Manual (Page 62)

62 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Chapter 7: ML561 Hardware-Simulation Correlation R
Figure 7-6: DDR2 Component Write HW Measurement - Waveform Scope Shot at Probe Point
(DDR2 Memory Via)
UG199_c7_06_071107
Figure 7-7: DDR2 Component Write Correlation - Waveform Scope Shot at Probe Point (Slow Corner)
65.000 75.000 85.000 95.000 105.000
-200.0
Time (ns)
Voltage (mV)
0.000
200.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
1800.0
Probe 3:C9.1 (at pin)
UG199_c7_07_070907