Summary and recommendations – Xilinx Virtex-5 FPGA ML561 User Manual
Page 91
Virtex-5 FPGA ML561 User Guide
91
UG199 (v1.2.1) June 15, 2009
Summary and Recommendations
R
Summary and Recommendations
The first objective of this exercise is to establish correlation between hardware
measurements and the simulation at the probe point. The intention was to validate the
simulation model for the targeted signal. The degree of correlation achieved is looked at in
terms of absolute difference as well as relative percentage. The relative percentage
differences are presented in terms of unit interval (UI) for timing characteristics and in
terms of VREF voltage for the voltage margin characteristics.
Correlation simulation is performed under ideal conditions, that is, the stimulus is
generated without any jitter. On the other hand, the hardware measurements are subject to
jitter (which tends to increase ISI), board-level power fluctuation (which can affect the eye
amplitude), and stability of the probing station. Thus some correlation differences are
expected. The user ultimately uses his or her own judgment to account for these
differences, and adjusts the values extrapolated for quality of signal at the receiver IOB.
contains this information for all six test signals.
There are varying degrees of correlation differences among the six test signals. In general,
there is a good match between hardware measurements and the correlation simulation,
except for some yet-to-be analyzed differences, for example, DDR2 DIMM Write DVW and
QDRII read noise margin.
The remainder of this section summarizes the extrapolation results of the data bit interface
for all six memory operations on the ML561 board. The measure of SI characteristics of
each signal is determined by the worst-case extrapolation measurement from among the
simulations with drivers at slow-weak and fast-strong corners. The values chosen between
these two corner cases are:
•
Minimum of DVW, noise margin, and overshoot/undershoot margin
•
Maximum of ISI
Table 7-15:
Summary of Correlation Differences: Hardware vs. Simulation
Operation
ΔDVW
(% UI
(1)
)
ΔISI
(% UI)
Noise Margin
(% VREF)
Overshoot /
Undershoot Margin
(% VREF)
DDR2 Component Write
40 ps
(2.6%)
47 ps
(3.2%)
98 mV
(10.9%)
69 mV
(7.6%)
DDR2 Component Read
0 ps
(0%)
43 ps
(2.9%)
6 mV
(0.7%)
244 mV
(17.2%)
DDR2 DIMM Write
218 ps
(14.5%)
366 ps
(24.5%)
112 mV
(12.6%)
2 mV
(0.3%)
DDR2 DIMM Read
39 ps
(2.6%)
44 ps
(2.9%)
90 mV
(10.0%)
208 mV
(23.1%)
QDRII Write
10 ps
(0.6%)
107 ps
(6.4%)
2 mV
(0.3%)
85 mV
(9.4%)
QDRII Read
106 ps
(6.4%)
27 ps
(1.6%)
386 mV
(31.8%)
50 mV
(5.6%)
Notes:
1. Unit Interval (UI): 1.5 ns for DDR2 and 1.67 ns for QDRII. VREF = 0.9V for DDR2 and QDRII.