Xilinx Virtex-5 FPGA ML561 User Manual
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Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Preface: About This Guide
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Hardware Measurements
These measurements are the actual real-time measurements of an eye diagram and a
segment of the test pattern (PRBS6) waveform captured on ML561 hardware at the
designated probe point using an Agilent scope.
Inter-Symbol Interference
(ISI)
As the frequency of operation increases, the signal delay is affected by the data pattern
that precedes the current data bit. This is called the inter-symbol interference (ISI) effect.
All testing is performed with a pseudo-random bitstream (PRBS) of order 6, that is,
PRBS6. ISI is the jitter represented by the eye at all four voltage thresholds. The worst
of the following two sum values are listed in this table:
• Sum of ISI at VIH(ac)-min and VIH(dc)-min
• Sum of ISI at VIL(ac)-max and VIL(dc)-max
Noise Margin
This is the noise margin available at the receiver. Measurements are taken at the AC
voltage levels as the minimum vertical opening of the eye in the vicinity of the center
of the bit period. Ideally, the input voltage needs to remain above the DC voltage
specifications. However, by considering the AC voltage specifications for the nominal
voltage level for VREF, these measurements are more conservative values that also
include the effects of VREF variations.
• VIH margin: Difference between the top of the eye opening and VIH(ac)-min
• VIL margin: Difference between VIL(ac)-max and the bottom of the eye opening
These measurements are performed in stand-alone fashion for the signal under test.
Thus no consideration of crosstalk or Simultaneously Switching Output (SSO) effects
are accounted for.
Overshoot / Undershoot
Margin
Overshoot margin is the difference between the maximum allowable VIH per JEDEC
specification and the maximum amplitude of the measured eye. Similarly, undershoot
margin is the difference between the minimum amplitude of the measured eye and the
minimum allowable VIL value per JEDEC specification. For both SSTL18 and 1.8V
HSTL specifications:
• VIH(max) < (VDDQ + 300 mV) = (1.8 + 0.3)V = 2.1V
• VIL(min) > -300 mV = 0.3V
Note:
VIH(max) must not exceed 1.9V for all Micron Parts.
Simulation Correlation
The BoardSim utility of the HyperLynx simulator is used to extract the IBIS schematics
of the same signal net for which hardware measurements are made. To replicate the
hardware measurement probe set up at the probe point, a 0.5 pF probe capacitance is
added based on Agilent probe loading specifications to the extracted IBIS schematics of
the memory signal. For the FPGA devices soldered on the ML561 board under test, the
process corner (slow, typical, or fast) is not known. Thus simulation is performed for all
three corners (slow-weak, typical, and fast-strong), and the results of the case that best
fits with hardware measurement is selected for tabulation.
VIH(ac)-min
This term is the minimum input level at which the receiver must recognize input logic
High.
VIH(dc)-min
When the input signal reaches VIH(ac)-min, the receiver continues to interpret the
input as a logic High as long as the signal remains above this voltage. (This parameter
is basically the hysteresis for a logic ‘1’.)
VIL(ac)-max
This term is the maximum input level at which the receiver must recognize input logic
Low.
VIL(dc)-max
When the input signal reaches VIL(ac)-max, the receiver continues to interpret the input
as a logic Low as long as the signal remains below this voltage. (This parameter is
basically the hysteresis for logic ‘0’.)