Xilinx Virtex-5 FPGA ML561 - Manual (Page 71)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 71
UG199 (v1.2.1) June 15, 2009
Signal Integrity Correlation Results R
DDR2 DQ is a bidirectional signal. To perform hardware measurements for a Write
operation that is not interrupted by a Read response or a Refresh operation, the testbench
on FPGA2 is controlled by DIP switches (SW1) as indicated in
Table 7-8 .
Table 7-7: DDR2 DIMM Write Operation Correlation Results
Measurement
DVW
(%UI)
ISI
(% UI)
Noise Margin
(VIH + VIL) = Total
(% of VREF)
Overshoot / Undershoot
Margin
(% of VREF)
Hardware at Probe
Point 942 ps
(62.8%)
(300 + 200) = 500 ps
(33.3%)
(110 + 100) = 210 mV
(23.3%)
(620 + 620) = 1240 mV
(137.7%)
Simulation correlation
at memory via (C13)
slow-weak corner
1.16 ns
(77.3%)
(80 + 54) = 134 ps
(8.9%)
(172 + 150) = 322 mV
(35.9%)
(606 + 636) =1242 mV
(138%)
Correlation Delta:
HW vs. Simulation
218 ps
(14.5%)
366 ps
(24.4%)
112 mV
(12.6%)
2 mV
(0.3%)
Extrapolation at IOB
slow-weak corner 1.23 ns
(82%)
(85 + 32) = 117 ps
(7.8%)
(178 + 137) = 315 mV
(35.0%)
(604 + 632) = 1236 mV
(137.3%)
Extrapolation at IOB
fast-strong corner 1.32 ns
(88%)
(54 + 46) = 100 ps
(6.7%)
(146 + 107) = 253 mV
(28.1%)
(457 + 524) = 981 mV
(109.0%)
Table 7-8: DIP[1:2] Settings
Setting Description
2’b00 or 2’b11 Normal alternating Write/Read sequence
2’b01 Write only, Refresh disabled
2’b10 Write once, then Read only, Refresh disabled