Xilinx Virtex-5 FPGA ML561 - Manual (Page 55)

Virtex-5 FPGA ML561 User Guide www.xilinx.com 55
UG199 (v1.2.1) June 15, 2009
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Chapter 7
ML561 Hardware-Simulation
Correlation
This chapter contains the following sections:
• “Introduction”
• “Test Setup”
• “Signal Integrity Correlation Results”
• “Summary and Recommendations”
• “How to Generate a User-Specific FPGA IBIS Model”
Introduction
Signal integrity (SI) simulation is a very powerful tool that predicts the quality of signal at
the receiver. The quality of signal at the I/O buffer of the receiver device is most important
to the system designer. The observation point is buried within the IC device and is not
accessible for attaching a physical probe. This signal can only be simulated. It cannot be
measured on the hardware with an oscilloscope.
Signals can only be measured on hardware at the via probe points of a printed circuit board
(PCB) near the receiver device. For a high level of confidence in the SI simulation results, it
is necessary to develop and validate the simulation model to get a good correlation with
the hardware measurements at the probe points. When the correlation is obtained, the
same simulation model is used to extrapolate and accurately predict the signal quality at
the I/O buffer of the receiver device for the two significant corner driver conditions: slow-
weak and fast-strong.
The Virtex-5 FPGA ML561 Development Board implements five different memory
interfaces:
• 32-bit DDR2 component
• 144-bit DDR2 DIMM
• 72-bit QDRII SRAM
• 32-bit DDR component
• 36-bit RLDRAM II
Each of these interfaces consists address, control, clock, data, and strobe signals. The
ML561 board has over 500 unique signals.
DDR2 SDRAMs and QDRII SRAM represent the large majority of Virtex-5 FPGA memory
applications. The dual data rate (DDR) data bits are the most critical signals to analyze.
This chapter presents SI analysis for only six representative data bit signals. The procedure