Xilinx Virtex-5 FPGA ML561 - Manual (Page 104)

104 www.xilinx.com Virtex-5 FPGA ML561 User Guide
UG199 (v1.2.1) June 15, 2009
Appendix A: FPGA Pinouts R
DDR2 DIMM Wide Interface (cont.)
DDR2_DIMM_DQ_BY15_B5 AD5 DDR2_DIMM_DQ_CB8_15_B4 N7
DDR2_DIMM_DQ_BY15_B6 AD4 DDR2_DIMM_DQ_CB8_15_B5 N8
DDR2_DIMM_DQ_BY15_B7 Y8 DDR2_DIMM_DQ_CB8_15_B6 M5
DDR2_DIMM_DQ_BY8_B0 G13 DDR2_DIMM_DQ_CB8_15_B7 M6
DDR2_DIMM_DQ_BY8_B1 F13 DDR2_DIMM_DQS_BY10_L_N J9
DDR2_DIMM_DQ_BY8_B2 N9 DDR2_DIMM_DQS_BY10_L_P J10
DDR2_DIMM_DQ_BY8_B3 N10 DDR2_DIMM_DQS_BY11_L_N J7
DDR2_DIMM_DQ_BY8_B4 E13 DDR2_DIMM_DQS_BY11_L_P H7
DDR2_DIMM_DQ_BY8_B5 E12 DDR2_DIMM_DQS_BY12_L_N U7
DDR2_DIMM_DQ_BY8_B6 L9 DDR2_DIMM_DQS_BY12_L_P T8
DDR2_DIMM_DQ_BY8_B7 M10 DDR2_DIMM_DQS_BY13_L_N AF6
DDR2_DIMM_DQ_BY9_B0 A13 DDR2_DIMM_DQS_BY13_L_P AE7
DDR2_DIMM_DQ_BY9_B1 H9 DDR2_DIMM_DQS_BY14_L_N V7
DDR2_DIMM_DQ_BY9_B2 H10 DDR2_DIMM_DQS_BY14_L_P W7
DDR2_DIMM_DQ_BY9_B3 C12 DDR2_DIMM_DQS_BY15_L_N AF5
DDR2_DIMM_DQ_BY9_B4 D12 DDR2_DIMM_DQS_BY15_L_P AG5
DDR2_DIMM_DQ_BY9_B5 J11 DDR2_DIMM_DQS_BY8_L_N C13
DDR2_DIMM_DQ_BY9_B6 K11 DDR2_DIMM_DQS_BY8_L_P B13
DDR2_DIMM_DQ_BY9_B7 D11 DDR2_DIMM_DQS_BY9_L_N K9
DDR2_DIMM_DQ_CB8_15_B0 20 P5 DDR2_DIMM_DQS_BY9_L_P K8
DDR2_DIMM_DQ_CB8_15_B1 N5 DDR2_DIMM_DQS_CB8_15_L_N R8
DDR2_DIMM_DQ_CB8_15_B2 L6 DDR2_DIMM_DQS_CB8_15_L_P R7
DDR2_DIMM_DQ_CB8_15_B3 M7
DDR2 DIMM Miscellaneous Signals
DDR2_DIMM1_CNTL_PAR G27 DDR2_DIMM3_CNTL_PAR AA28
DDR2_DIMM1_CNTL_PAR_ERR H27 DDR2_DIMM3_CNTL_PAR_ERR AG28
DDR2_DIMM1_NC_019 K24 DDR2_DIMM3_NC_019 AK29
DDR2_DIMM1_NC_102 L24 DDR2_DIMM3_NC_102 AJ29
DDR2_DIMM2_CNTL_PAR AD26 DDR2_DIMM4_CNTL_PAR AG8
DDR2_DIMM2_CNTL_PAR_ERR AD25 DDR2_DIMM4_CNTL_PAR_ERR AH8
DDR2_DIMM2_NC_019 AK28 DDR2_DIMM4_NC_019 AL10
DDR2_DIMM2_NC_102 AK27 DDR2_DIMM4_NC_102 AE8
Table A-2: FPGA #2 Pinout (Continued)
Signal Name Pin Signal Name Pin