Xilinx 1000BASE-X User Manual
User guide
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Table of contents
Document Outline
- LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
- About This Guide
- Introduction
- Core Architecture
- Generating and Customizing the Core
- Designing with the Core
- Using the Client-side GMII Data Path
- The Ten-Bit Interface
- 1000BASE-X with RocketIO Transceivers
- SGMII / Dynamic Standards Switching with RocketIO Transceivers
- Configuration and Status
- Auto-Negotiation
- Dynamic Switching of 1000BASE-X and SGMII Standards
- Constraining the Core
- Required Constraints
- Device, Package, and Speedgrade Selection
- I/O Location Constraints
- Placement Constraints
- Virtex-II Pro RocketIO MGTs for 1000BASE-X Constraints
- Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints
- Virtex-4 RocketIO MGTs for 1000BASE-X Constraints
- Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints
- Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints
- Virtex-5 RocketIO GTP Transceivers for SGMII or Dynamic Standards Switching Constraints
- Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints
- Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints
- Ten-Bit Interface Constraints
- Constraints When Implementing an External GMII
- Understanding Timing Reports for Setup/Hold Timing
- Required Constraints
- Interfacing to Other Cores
- Special Design Considerations
- Implementing the Design
- Core Verification, Compliance, and Interoperability
- Core Latency
- Calculating the DCM Fixed Phase Shift Value
- 1000BASE-X State Machines
- Rx Elastic Buffer Specifications
- Debugging Guide