Xilinx 1000BASE-X - Manual (Page 103)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 103
UG155 March 24, 2008
RocketIO Logic with the Fabric Rx Elastic Buffer R
Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching
The core is designed to integrate with the Virtex-5 RocketIO GTP transceiver. The
connections and logic required between the core and GTP transceiver are illustrated in
Figure 8-5 –the signal names and logic in the figure precisely match those delivered with
the example design when a GTP transceiver is used.
Note: A small logic shim (included in the block” level wrapper) is required to convert between the
port differences between the Virtex-II Pro and Virtex-5 RocketIO GTP transceiver. This is not
illustrated in
Figure 8-5 .
A GTP tile consists of a pair of transceivers. For this reason, the GTP transceiver wrapper
delivered with the core will always contain two GTP transceiver instantiations, even if
only a single GTP is in use.
Figure 8-5 illustrates only a single GTP transceiver for clarity.
The 125 MHz differential reference clock is routed to the GTP transceiver, which is
configured to output a version of this clock on the REFCLKOUT port, and once placed onto
global clock routing can be used by all core logic. This clock is input back into the GTP
transceiver on the user interface clock port txusrclk and txusrclk2.
It can be seen from Figure 8-5 that the Rx Elastic Buffer is implemented in the FPGA fabric
between the GTP transceiver and the core; this replaces the Rx Elastic Buffer in the GTP
transceiver.
This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as
large as the one present in the GTP transceiver. It is able to cope with larger frame sizes
before clock tolerances accumulate and result in emptying or filling of the buffer. This is
necessary to guarantee SGMII operation at 10 Mbps where each frame size is effectively
100 times larger than the same frame would be at 1 Gbps because each byte is repeated 100
times (see
“Designing with Client-side GMII for the SGMII Standard,” page 59 ).
With this fabric Rx Elastic Buffer implementation, data is clocked out of the GTP
transceiver synchronously to rxrecclk0. This clock can be placed on a BUFR component
and is used to synchronize the transfer of data between the GTP and the Elastic Buffer, as
illustrated in
Figure 8-5 . See also “Virtex-5 RocketIO GTP Transceivers for SGMII or
Dynamic Standards Switching Constraints,” page 167 .
Virtex-5 RocketIO GTP Wizard
The two wrapper files immediately around the GTP transceiver pair,
rocketio_wrapper_gtp_tile
and rocketio_wrapper_gtp (see Figure 8-5 ), are
generated from the RocketIO GTP Wizard. These files apply all the gigabit Ethernet
attributes. Consequently, these files can be regenerated by customers and therefore be
easily targeted at ES or Production silicon. Note that this core targets production silicon.
The CORE Generator log file (XCO file) which was created when the RocketIO GTP Wizard
project was generated is available in the following location:
<project_directory>/<component_name>/example_design/transceiver/
rocketio_wrapper_gtp.xco
This file can be used as an input to the CORE Generator to regenerate the RocketIO
wrapper files. The XCO file itself contains a list of all of the GTP Wizard attributes which
were used. For further information, please refer to the Virtex-5 RocketIO GTP Wizard Getting
Started Guide (UG188) and the CORE Generator Guide, at
www.xilinx.com/support/software_manuals.htm