Xilinx 1000BASE-X - Manual (Page 225)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 225
UG155 March 24, 2008
Clock Correction R
Idle Character Removal at 100 Mbps (SGMII)
At SGMII, 100 Mbps, each byte is repeated 10 times. This also applies to the interframe gap
period. For this reason, the minimum of 8 bytes for the 1 Gbps case corresponds to a
minimum of 80 bytes for the 100 Mbps case.
Additionally, the majority of characters in this 80-byte interframe-gap period are going to
be the /I2/ clock correction characters. Because of the clock correction circuitry design, a
minimum of 20 /I2/ code groups will be available for removal. This translates into 40
bytes, giving a maximum run size of 40 x 5000 = 200000 bytes. Because each byte at 100
Mbps is repeated ten times, this corresponds to an Ethernet frame size of 20000 bytes, the
same size as the 1 Gbps case.
So in summary, at 100Mbps, for any frame size of 20000 bytes or less, it can still be assumed
that the Elastic Buffer will return to half full occupancy before the start of the next frame.
However, a frame size of 20000 is larger than can be received in the RocketIO Elastic Buffer
(see
“Rx Elastic Buffers: Depths and Maximum Frame Sizes” ). Only the SGMII fabric Rx
Elastic buffer is large enough.
Idle Character Removal at 10 Mbps (SGMII)
Using a similar argument to the 100 Mbps case, it can be shown that clock correction
circuitry can also cope with a frame size up to 20000 bytes. However, this is larger than the
maximum frame size for any Elastic Buffer provided with the core (see
“Rx Elastic Buffers:
Depths and Maximum Frame Sizes” ).