Xilinx 1000BASE-X - Manual (Page 118)

118 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 9: Configuration and Status R
known by the MDIO master (in this case an Ethernet MAC), and placed into the PHYAD
field of the MDIO frame (see
“MDIO Transactions” ).
The PHYAD field for an MDIO frame is a 5-bit binary value capable of addressing 32
unique addresses. However, every MDIO slave must respond to physical address 0. This
requirement dictates that the physical address for any particular PHY must not be set to 0
to avoid MDIO contention. Physical Addresses 1 through to 31 can be used to connect up
to 31 PHY devices onto a single MDIO bus.
Physical Address 0 can be used to write a single command that is obeyed by all attached
PHYs, such as a reset or power-down command.
Register Address (REGAD)
Having targeted a particular PHY using PHYAD, the individual configuration or status
register within that particular PHY must now be addressed. This is achieved by placing the
individual register address into the REGAD field of the MDIO frame (see
“MDIO
Transactions” ).
The REGAD field for an MDIO frame is a 5-bit binary value capable of addressing 32
unique addresses. The first 16 of these (registers 0 to 15) are defined by the IEEE 802.3. The
remaining 16 (registers 16 to 31) are reserved for PHY vendors own register definitions.
For details of the register map of PHY layer devices and a more extensive description of the
operation of the MDIO Interface, see IEEE 802.3-2002.
Connecting the MDIO to an Internally Integrated STA
The MDIO ports of the Ethernet 1000BASE-X PCS/PMA or SGMII core can be connected to
the MDIO ports of an internally integrated Station Management (STA) entity, such as the
MDIO port of the 1-Gigabit Ethernet MAC core (see
“Integrating with the 1-Gigabit
Ethernet MAC Core,” page 179 ) or the Tri-Mode Ethernet MAC core (see “Integrating with
the Tri-Mode Ethernet MAC Core,” page 185 ).
Connecting the MDIO to an External STA
Figure 9-4 shows the MDIO ports of the Ethernet 1000BASE-X PCS/PMA or SGMII core
connected to the MDIO of an external STA entity. In this situation, mdio_in, mdio_out,
and mdio_tri must be connected to a Tri-State buffer to create a bidirectional wire, mdio.
This Tri-State buffer can either be external to the FPGA, or internally integrated by using an
IOB IOBUF component with an appropriate SelectIO™ standard suitable for the external
PHY.