Figure 7-1 – Xilinx 1000BASE-X User Manual
Page 80
80
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 7: 1000BASE-X with RocketIO Transceivers
R
Figure 7-1:
1000BASE-X Connection to a Virtex-II Pro MGT
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
Virtex-II Pro
RocketIO
(GT_ETHERNET_1)
BREFCLK2
TXUSRCLK
TXUSRCLK2
RXUSRCLK
RXUSRCLK2
userclk
userclk2
DCM
CLKIN CLK0
FB
BUFG
CLK2X180
BUFG
userclk (62.5MHz)
userclk2 (125MHz)
IPAD
IBUFGDS
IOB LOGIC
brefclkp
IPAD
brefclkn
brefclk (62.5MHz)
dcm_locked
LOCKED
rxbufstatus[1:0]
rxchariscomma
rxcharisk
rxclkcorcnt[2:0]
rxdata[7:0]
rxdisperr
powerdown
txchardispmode
txchardispval
txcharisk
txdata[7:0]
enablealign
mgt_tx_reset
mgt_rx_reset
RXRESET
TXRESET
RXBUFSTATUS[1:0]
RXCHARISCOMMA
RXCHARISK
RXCLKCORCNT[2:0]
RXDATA[7:0]
RXDISPERR
LOOPBACK[1:0]
POWERDOWN
TXCHARDISPMODE
TXCHARDISPVAL
TXCHARISK
TXDATA[7:0]
BREFCLK
REFCLK2
REFCLK
REFCLKSEL
NC
NC
NC
GND
ENPCOMMAALIGN
ENMCOMMAALIGN
D
Q
RXRECCLK
RXPOLARITY
TXPOLARITY
TXFORCECRCERR
TXINHIBIT
GND
GND
component_name_block
(Block Level from
example design)