Xilinx 1000BASE-X - Manual (Page 51)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 51
UG155 March 24, 2008
Design Guidelines R
Write an HDL Application
After reviewing the example design delivered with the core, write an HDL application that
uses single or multiple instances of the block level module for the Ethernet 1000BASE-X
PCS/PMA or SGMII core. Client-side interfaces and operation of the core are described in
Chapter 5, “Using the Client-side GMII Data Path.” See the following information for
additional details:
•
Using the Ethernet 1000BASE-X PCS/PMA or SGMII core in conjunction with the
1-Gigabit Ethernet MAC core in
“Integrating with the 1-Gigabit Ethernet MAC Core,”
page 179 .
•
Using the Ethernet 1000BASE-X PCS/PMA or SGMII core in conjunction with the Tri-
Mode Ethernet MAC core in
“Integrating with the Tri-Mode Ethernet MAC Core,”
page 185 .
Synthesize your Design
Synthesize your entire design using the desired synthesis tool. The Ethernet 1000BASE-X
PCS/PMA or SGMII core is pre-synthesized and delivered as an NGC netlist—for this
reason, it appears as a black box to synthesis tools.
Create a Bitstream
Run the Xilinx tools map, par, and bitgen to create a bitstream that can be downloaded to
a Xilinx device. The UCF produced by the CORE Generator should be used as the basis for
the user UCF and care must be taken to constrain the design correctly. See
Chapter 12,
“Constraining the Core” for more information.
Simulate and Download your Design
After creating a bitstream that can be downloaded to a Xilinx device, simulate the entire
design and download it to the desired device.
Know the Degree of Difficulty
An Ethernet 1000BASE-X PCS/PMA or SGMII core is challenging to implement in any
technology and as such, all Ethernet 1000BASE-X PCS/PMA or SGMII core applications
require careful attention to system performance requirements. Pipelining, logic mapping,
placement constraints, and logic duplication are all methods that help boost system
performance.
Review Table 4-1 to determine the relative level of difficulty associated with different
designs. This relates to meeting the core’s required system clock frequency of 125 MHz.
Table 4-1: Degree of Difficulty for Various Implementations
Device Family Difficulty
Virtex-II Easy
Virtex-II Pro Easy
Virtex-4 Easy
Virtex-5 Easy
Spartan™-3 Difficult