Xilinx 1000BASE-X - Manual (Page 221)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 221
UG155 March 24, 2008
Rx Elastic Buffers: Depths and Maximum Frame Sizes R
Virtex-4 FX
Consider the Virtex-4 FX case also illustrated in Figure E-1 . The thresholds are different to
that of the Virtex-II Pro/Virtex-5 case, but the overall size of the buffer is the same. Instead
of the half full point, there are configurable clock correction thresholds. During the
interframe gap, clock correction will attempt to restore the occupancy to within these two
thresholds.
However, by setting both CLK_COR_MAX_LAT and CLK_COR_MIN_LAT thresholds to the
same value, symmetrically between overflow and underflow marks, it is possible to obtain
the same figures as per the Virtex-II Pro/Virtex-5 analysis. For this reason, by adjusting the
threshold attributes accordingly,
Table E-1 is also applicable.