Xilinx 1000BASE-X - Manual (Page 121)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 121
UG155 March 24, 2008
Management Registers R
0.13 Speed
Selection
(LSB) Always returns a 0 for this bit.
Together with bit 0.6, speed selection
of 1000 Mbps is identified Returns 0 0
0.12 Auto-
Negotiation
Enable 1 = Enable Auto-Negotiation
Process
0 = Disable Auto-Negotiation
Process
Read/write 1
0.11 Power Down 1 = Power down
0 = Normal operation
With the PMA option, when set to ’1’
the RocketIO transceiver is placed in
a low-power state. This bit requires a
reset (see bit 0.15) to clear.
With the TBI version this register bit
has no effect.
Read/ write 0
0.10 Isolate 1 = Electrically Isolate PHY from
GMII
0 = Normal operation
Read/write 1
0.9 Restart Auto-
Negotiation 1 = Restart Auto-Negotiation
Process
0 = Normal Operation
Read/write
Self clearing
0
0.8 Duplex Mode Always returns a ‘1’ for this bit to
signal Full-Duplex Mode. Returns 1 1
0.7 Collision Test Always returns a ‘0’ for this bit to
disable COL test. Returns 0 0
0.6 Speed
Selection
(MSB) Always returns a ‘1’ for this bit.
Together with bit 0.13, speed
selection of 1000 Mbps is identified. Returns 1 1
0.5 Unidirectiona
l Enable Enable transmit regardless of
whether a valid link has been
established. Read/ write 0
0.4:0 Reserved Always return 0s, writes ignored. Returns 0s 00000
Table 9-3: Control Register (Register 0) (Continued)
Bit(s) Name Description Attributes
Default
Value