Clock correction – Xilinx 1000BASE-X User Manual
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Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Appendix E: Rx Elastic Buffer Specifications
R
Note that this analysis assumes that the buffer is approximately at the half-full level at the
start of the frame reception. As illustrated, there are two locations of uncertainty above and
below the exact half-full mark of 16. This is as a result of the clock correction decision, and
is based across an asynchronous boundary.
Since there is a worst-case scenario of 1 clock edge difference every 5000 clock periods, the
maximum number of clock cycles (bytes) that can exist in a single frame passing through
the buffer before an error occurs is:
5000 x 12 = 60000 bytes
This translates into a maximum frame size of 60000 bytes.
Clock Correction
The calculations in all previous sections assumes that the Rx Elastic Buffers are restored to
approximately half occupancy at the start of each frame. This is achieved by the elastic
buffer performing clock correction during the interframe gaps either by inserting or
removing Idle characters as required.
•
If the Rx Elastic Buffer is emptying during frame reception, there are no restrictions on
the number of Idle characters that can be inserted due to clock correction. The
occupancy will be restored to half full and the assumption holds true.
•
If the Rx Elastic Buffer is filling during frame reception, Idle characters need to be
removed. Restrictions that need to be considered are described in the following
sections.
Idle Character Removal at 1Gbps (1000BASE-X and SGMII)
The minimum number of clock cycles that may be presented to an Ethernet receiver,
according to the IEEE 802.3 specification, is 64-bit times at any Ethernet speed. At 1 Gbps
1000BASE-X and SGMII, this corresponds to 8 bytes (8 clock cycles) of interframe gap.
However, an interframe gap consists of a variety of code groups, namely /T/, /R/, /I1/
and /I2/ characters (please refer to
Appendix D, “1000BASE-X State Machines”
). Of these,
only /I2/ can be used as clock correction characters.
In a minimum interframe gap at 1 Gbps, we can only assume that two /I2/ characters are
available for removal. This corresponds to 4 bytes of data.
Looking at this from another perspective, 4 bytes of data will need to be removed in an
elastic buffer (which is filling during frame reception) for a frame which is 5000 x 4 = 20000
bytes in length. So if the frame being received is 20000 bytes in length or shorter, at 1 Gbps,
we can assume that the occupancy of the elastic buffer will always self correct to half full
before the start of the subsequent frame.
For frames which are longer than 20000 bytes, the assumption that the elastic buffer will be
restored to half full occupancy does not hold true. For example, for a long stream of 250000
byte frames, each separated by a minimum interframe gap, the Rx Elastic Buffer will
eventually fill and overflow. This is despite the 250000 byte frame length being less than
the maximum frame size calculated in the
“Rx Elastic Buffers: Depths and Maximum
section.
However, since the legal maximum frame size for Ethernet frames is 1522 bytes (for a
VLAN frame), idle character removal restrictions are not usually an issue.