Figure 13-8, Integrating with the tri-mode ethernet mac core – Xilinx 1000BASE-X User Manual
Page 191
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
191
UG155 March 24, 2008
Integrating with the Tri-Mode Ethernet MAC Core
R
Figure 13-8:
Tri-Speed Ethernet MAC Extended to Use an SGMII in Virtex-4
Tri-Speed
Ethernet
MAC
LogiCORE
phyemacrxd[7:0]
phyemacrxdv
phyemacrxer
emacphytxd7:0]
emacphytxen
emacphytxer
emacphymclkout
phyemacmdin
emacphymdout
emacphymdtri
Ethernet
1000BASE-X
PCS/PMA
or SGMII
LogiCORE
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
mdc
mdio_in
mdio_out
mdio_tri
no
connection
userclk2
RocketIO I/F
gmii_rxd_out[7:0]
gmii_rx_dv_out
gmii_rx_er_out
gmii_txd_in[7:0]
gmii_tx_en_in
gmii_tx_er_in
gmii_rxd_in[7:0]
gmii_rx_dv_in
gmii_rx_er_in
gmii_txd_out[7:0]
gmii_tx_en_out
gmii_tx_er_out
clk125m
SGMII Adaptation
module
sgmii_clk_en
speed_is_10_100
speed_is_100
speedis10100
speedis100
rxgmiimiiclk
txgmiimiiclk
corehassgmii
VCC
clientemacrxenable
clientemactxenable
sgmii_clk_r
NC
Virtex-4
GT11
RocketIO
(used)
IPAD
brefclkp
(250MHz)
IPAD
brefclkn
(250MHz)
Virtex-4
GT11CLK_MGT
MGTCLKP
MGTCLKN
SYNCLK1OUT
REFCLK1
TXUSRCLK
TXUSRCLK2
userclk2
(125 MHz)
synclk1
(250MHz)
userclk
‘0’
BUFG
TXOUTCLK1
component_name_block
(Block Level from example design)