Xilinx 1000BASE-X - Manual (Page 129)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 129
UG155 March 24, 2008
Management Registers R
Register 16: Vendor-Specific Auto-Negotiation Interrupt Control
1000BASE-X Standard Without the Optional Auto-Negotiation
It is not the intention of this document to fully describe the 1000BASE-X PCS Registers. See
clauses 37 and 22 of the IEEE 802.3 Specification for further information.
Registers at undefined addresses are read-only and return 0s.
MDIO Register 16: Vendor Specific Auto-Negotiation Interrupt Control
Table 9-12: Vendor Specific Register: Auto-Negotiation Interrupt Control Register
(Register 16)
Bit(s) Name Description Attributes Default Value
16.15:2 Reserved Always return 0s returns 0s 00000000000000
16.1 Interrupt
Status 1 = Interrupt is asserted
0 = Interrupt is not asserted
If the interrupt is enabled, this bit is
asserted on the completion of an
Auto-Negotiation cycle; it is only
cleared by writing ‘0’ to this bit.
If the Interrupt is disabled, the bit is
set to ‘0.’
NOTE: the an_interrupt port of
the core is wired to this bit.
read/
write
0
16.0 Interrupt
Enable 1 = Interrupt enabled
0 = Interrupt disabled
read/
write
1
15 0
Reg 16
RESER
VED
1 2
INTERR
UPT ST
A
TUS
INTERR
UPT ENABLE
Table 9-13: MDIO Registers for 1000BASE-X without Auto-Negotiation
Register Address Register Name
0 Control Register
1 Status Register
2,3 PHY Identifier
15 Extended Status Register