Xilinx 1000BASE-X - Manual (Page 79)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 79
UG155 March 24, 2008
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Chapter 7
1000BASE-X with RocketIO
Transceivers
This chapter provides general guidelines for creating 1000BASE-X designs that use
RocketIO transceivers for Virtex-II Pro, Virtex-4, and Virtex-5 devices. Information about
RocketIO transceiver and core logic in all supported device families is provided, as well as
information about designs requiring multiple instantiations of the core. Note that clock
sharing should occur whenever possible to save device resources.
RocketIO Transceiver Logic
The example is split between two discrete hierarchical layers, as illustrated in Figure 4-1 .
The block level is designed so that it can be instantiated directly into customer designs and
provides the following functionality:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to a Virtex-II Pro, Virtex-4, or Virtex-5
RocketIO transceiver
The logic implemented in the block level is illustrated in all the figures in this chapter.
Virtex-II Pro Devices
The core is designed for seamless integration with the Virtex-II Pro RocketIO Multi-Gigabit
Transceiver (MGT).
Figure 7-1 illustrates the connections and logic required between the
core and the MGT—the signal names and logic in the figure precisely match those
delivered with the example design when an MGT is used.
Some modifications can be made to the MGT. For example, REFCLK may be used instead of
BREFCLK
. See the RocketIO Transceiver User Guide (UG024) for details.
The placement of the flip-flop that connects to ENMCOMMAALIGN and ENPCOMMAALIGGN is
important (see
Figure 7-1 ). For detailed information, see “Virtex-II Pro RocketIO MGTs for
1000BASE-X Constraints,” and the RocketIO Transceiver User Guide.
Note: The brefclk differential pair applied to the MGT is of frequency 62.5 MHz.