Xilinx 1000BASE-X - Manual (Page 194)

194 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 13: Interfacing to Other Cores R
Virtex-5 FXT Devices
Figure 13-10 illustrates the connections and clock management logic required to interface
the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in SGMII mode with the
Virtex-5 GTX) to the Tri-Mode Ethernet MAC core.
The following conditions apply.
•
The SGMII Adaptation module, as provided in the example design for the Ethernet
1000BASE-X PCS/PMA or SGMII core when generated to the SGMII standard, can be
used to interface the two cores.
•
If both cores have been generated with the optional management interface, the MDIO
port can be connected up to that of the Tri-Speed Ethernet MAC core, allowing the
MAC to access the embedded configuration and status registers of the Ethernet
1000BASE-X PCS/PMA or SGMII core.
•
Due to the Receiver Elastic Buffer, the entire GMII (transmitter and receiver paths) is
synchronous to a single clock domain. Therefore the txcoreclk and rxcoreclk
inputs of the Tri-Speed Ethernet MAC core can always be driven from the same clock
source. The entire design is synchronous to the 125 MHz reference clock derived from
the CLK2X180 output of the DCM.
Figure 13-10 illustrates the Tri-Mode Ethernet MAC core generated with the optional clock
enable circuitry. This is the most efficient way to connect the two cores together in terms of
clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for
more information.