Xilinx 1000BASE-X - Manual (Page 34)

34 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 2: Core Architecture R
MDIO Management Interface Pinout (Optional)
Table 2-3 describes the optional MDIO interface signals of the core used to access the PCS
Management Registers. These signals are typically connected to the MDIO port of a MAC
device, either off-chip or to an internally integrated MAC core. For more information, see
“Management Registers” in Chapter 9 .
Table 2-3: Optional MDIO Interface Signal Pinout
Signal Direction
Clock
Domain
Description
mdc Input N/A Management clock (<= 2.5 MHz).
mdio__in 1
1. These signals can be connected to a Tri-state buffer to create a bidirectional mdio signal suitable for
connection to an external MDIO controller (for example, an Ethernet MAC).
Input mdc Input data signal for communication with
MDIO controller (for example, an Ethernet
MAC). Tie high if unused.
mdio_out 1 Output mdc Output data signal for communication with
MDIO controller (for example, an Ethernet
MAC).
mdio_tri 1 Output mdc Tri-state control for MDIO signals; ‘0’ signals
that the value on mdio_out should be asserted
onto the MDIO interface.
phyad[4:0] Input N/A Physical Address of the PCS Management
register set. It is expected that this signal will be
tied off to a logical value.