Xilinx 1000BASE-X - Manual (Page 59)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 59
UG155 March 24, 2008
Designing with Client-side GMII for the SGMII Standard R
Designing with Client-side GMII for the SGMII Standard
Overview
When the core is generated for the SGMII standard, changes are made to the core that affect
the PCS Management Registers and the Auto-Negotiation function (see
“Select Standard”
in Chapter 3 ). However, the data path through both transmitter and receiver sections of the
core remains unchanged.
GMII Transmission
1 Gigabit per Second Frame Transmission
The timing of normal outbound frame transfer is illustrated in Figure 5-10 . At 1 Gbps
speed, the operation of the transmitter GMII signals remains identical to that described in
“Designing with the Client-side GMII for the 1000BASE-X Standard.”
100 Megabit per Second Frame Transmission
The operation of the core remains unchanged. It is the responsibility of the client logic (for
example, an Ethernet MAC) to enter data at the correct rate. When operating at a speed of
100 Mbps, every byte of the MAC frame (from preamble field to the Frame Check
Sequence field, inclusive) should each be repeated for 10 clock periods to achieve the
desired bit rate, as illustrated in
Figure 5-11 . It is also the responsibility of the client logic to
ensure that the interframe gap period is legal for the current speed of operation.
Figure 5-10: GMII Frame Transmission at 1 Gbps
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
preamble FCS
SFD
DO D1
userclk2
Figure 5-11: GMII Data Transmission at 100 Mbps
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
preamble SFD D0 D1
10 clock periods
userclk2