Xilinx 1000BASE-X - Manual (Page 181)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 181
UG155 March 24, 2008
Integrating with the 1-Gigabit Ethernet MAC Core R
Integration of the 1-Gigabit Ethernet MAC Using a RocketIO Transceiver
Virtex-II Pro Devices
Figure 13-2 illustrates the connections and clock management logic required to interface
the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode) to
the 1-Gigabit Ethernet MAC core.
Features of this configuration include:
•
Direct internal connections are made between the GMII interfaces between the two
cores.
Figure 13-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and
PMA Using a Virtex-II Pro MGT
1-Gigabit Ethernet
MAC
LogiCORE
gmii_rx_clk
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gtx_clk
mdc
mdio_in
mdio_out
mdio_tri
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
mdc
mdio_in
mdio_out
mdio_tri
Virtex-II Pro
RocketIO
(GT_ETHERNET_1)
brefclk
txusrclk
txusrclk2
rxusrclk
rxusrclk2
no
connection
userclk
userclk2
RocketIO I/F
DCM
CLKIN CLK0
FB
BUFG
CLK2X180
BUFG
userclk (62.5MHz)
userclk2 (125MHz)
IPAD
IBUFGDS
IOB LOGIC
brefclkp
IPAD
brefclkn
brefclk (62.5MHz)
component_name _block
(Block Level from example design)