Gmii iob constraints – Xilinx 1000BASE-X User Manual
Page 173
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
173
UG155 March 24, 2008
Required Constraints
R
############################################################
# GMII Clock period Constraints: please do not relax #
############################################################
NET "gmii_tx_clk_bufg" TNM_NET = "gmii_tx_clk";
TIMESPEC "ts_gmii_tx_clk" = PERIOD "gmii_tx_clk" 8000 ps HIGH 50 %;
GMII IOB Constraints
The following constraints target the flip-flops that are inferred in the top level HDL file for
the example design. Constraints are set to ensure that these are placed in IOBs.
############################################################
# GMII Transmitter Constraints: place flip-flops in IOB #
############################################################
INST "gmii_txd*" IOB = true;
INST "gmii_tx_en" IOB = true;
INST "gmii_tx_er" IOB = true;
############################################################
# GMII Receiver Constraints: place flip-flops in IOB #
############################################################
INST "gmii_rxd_obuf*" IOB = true;
INST "gmii_rx_dv_obuf" IOB = true;
INST "gmii_rx_er_obuf" IOB = true;
The GMII is a 3.3 volt signal level interface. The 3.3 volt LVTTL SelectIO standard is the
default for Virtex-II devices. The following constraints may be safely added. The 3.3 volt
LVTTL SelectIO standard is not the default for other families. Use the following constraints
and take into account the device IO Banking rules when fixing PADs.
INST "gmii_txd<?>" IOSTANDARD = LVTTL;
INST "gmii_tx_en" IOSTANDARD = LVTTL;
INST "gmii_tx_er" IOSTANDARD = LVTTL;
INST "gmii_rxd<?>" IOSTANDARD = LVTTL;
INST "gmii_rx_dv" IOSTANDARD = LVTTL;
INST "gmii_rx_er" IOSTANDARD = LVTTL;
INST "gmii_tx_clk" IOSTANDARD = LVTTL;
INST "gmii_rx_clk" IOSTANDARD = LVTTL;
In addition, the example design provides pad locking on the GMII for several families.
This is a provided as a guideline only; there are no specific I/O location constraints for this
core.