Document Outline

• LogiCORE™ IP Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
  • About This Guide
    • Guide Contents
    • Conventions
      • Typographical
      • Online Document
  • Introduction
    • About the Core
      • Designs Using RocketIO Transceivers
    • Recommended Design Experience
    • Additional Core Resources
      • Related Xilinx Ethernet Products and Services
      • Specifications
    • Technical Support
    • Feedback
      • Ethernet 1000BASE-X PCS/PMA or SGMII Core
      • Document
  • Core Architecture
    • System Overview
      • Ethernet 1000BASE-X PCS/PMA or SGMII Using A RocketIO Transceiver
      • Ethernet 1000BASE-X PCS/PMA or SGMII with Ten-Bit-Interface
    • Core Interfaces
      • Client Side Interface
      • Physical Side Interface
  • Generating and Customizing the Core
    • GUI Interface
      • Component Name
      • Select Standard
      • Core Functionality
      • SGMII/Dynamic Standard Switching Elastic Buffer Options
      • RocketIO Tile Configuration
    • Parameter Values in the XCO File
    • Output Generation
  • Designing with the Core
    • Design Overview
    • Design Guidelines
      • Generate the Core
      • Examine the Example Design Provided with the Core
      • Implement the Ethernet 1000BASE-X PCS/PMA or SGMII Core in Your Application
  • Using the Client-side GMII Data Path
    • Designing with the Client-side GMII for the 1000BASE-X Standard
      • GMII Transmission
      • GMII Reception
      • status_vector[4:0] signals
      • Using the Virtex-II Pro RocketIO Transceiver CRC Functionality
    • Designing with Client-side GMII for the SGMII Standard
      • Overview
      • GMII Transmission
      • GMII Reception
    • Using the GMII as an Internal Connection
    • Implementing External GMII
      • GMII Transmitter Logic
      • GMII Receiver Logic
  • The Ten-Bit Interface
    • Ten-Bit-Interface Logic
      • Transmitter Logic
      • Receiver Logic
    • Clock Sharing across Multiple Cores with TBI
  • 1000BASE-X with RocketIO Transceivers
    • RocketIO Transceiver Logic
      • Virtex-II Pro Devices
      • Virtex-4 FX Devices
      • Virtex-5 LXT and SXT Devices
      • Virtex-5 FXT Devices
    • Clock Sharing Across Multiple Cores with RocketIO
      • Virtex-II Pro Devices
      • Virtex-4 FX Devices
      • Virtex-5 LXT and SXT Devices
      • Virtex-5 FXT Devices
  • SGMII / Dynamic Standards Switching with RocketIO Transceivers
    • Receiver Elastic Buffer Implementations
      • Selecting the Buffer Implementation from the GUI
      • The Requirement for the FPGA Fabric Rx Elastic Buffer
      • The RocketIO Rx Elastic Buffer
    • RocketIO Logic using the RocketIO Rx Elastic Buffer
    • RocketIO Logic with the Fabric Rx Elastic Buffer
      • Virtex-II Pro Devices
      • Virtex-4 Devices for SGMII or Dynamic Standards Switching
      • Virtex-5 LXT or SXT Devices for SGMII or Dynamic Standards Switching
      • Virtex-5 FXT Devices for SGMII or Dynamic Standards Switching
    • Clock Sharing - Multiple Cores with RocketIO, Fabric Elastic Buffer
      • Virtex-II Pro Devices
      • Virtex-4 FX Devices
      • Virtex-5 LXT and SXT Devices
      • Virtex-5 FXT Devices
  • Configuration and Status
    • MDIO Management Interface
      • MDIO Bus System
      • MDIO Transactions
      • MDIO Addressing
      • Connecting the MDIO to an Internally Integrated STA
      • Connecting the MDIO to an External STA
    • Management Registers
      • 1000BASE-X Standard Using the Optional Auto-Negotiation
      • 1000BASE-X Standard Without the Optional Auto-Negotiation
      • SGMII Standard Using the Optional Auto-Negotiation
      • SGMII Standard without the Optional Auto-Negotiation
      • Both 1000BASE-X and SGMII Standards
    • Optional Configuration Vector
  • Auto-Negotiation
    • Overview of Operation
      • 1000BASE-X Standard
      • SGMII Standard
    • Setting the Configurable Link Timer
      • 1000BASE-X Standard
      • SGMII Standard
      • Simulating Auto-Negotiation
    • Using the Auto-Negotiation Interrupt
  • Dynamic Switching of 1000BASE-X and SGMII Standards
    • Typical Application
    • Operation of the Core
      • Selecting the Power-On / Reset Standard
      • Switching the Standard Using MDIO
      • Auto-Negotiation State Machine
      • Setting the Auto-Negotiation Link Timer
  • Constraining the Core
    • Required Constraints
      • Device, Package, and Speedgrade Selection
      • I/O Location Constraints
      • Placement Constraints
      • Virtex-II Pro RocketIO MGTs for 1000BASE-X Constraints
      • Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints
      • Virtex-4 RocketIO MGTs for 1000BASE-X Constraints
      • Virtex-4 RocketIO MGTs for SGMII or Dynamic Standards Switching Constraints
      • Virtex-5 RocketIO GTP Transceivers for 1000BASE-X Constraints
      • Virtex-5 RocketIO GTP Transceivers for SGMII or Dynamic Standards Switching Constraints
      • Virtex-5 RocketIO GTX Transceivers for 1000BASE-X Constraints
      • Virtex-5 RocketIO GTX Transceivers for SGMII or Dynamic Standards Switching Constraints
      • Ten-Bit Interface Constraints
      • Constraints When Implementing an External GMII
      • Understanding Timing Reports for Setup/Hold Timing
  • Interfacing to Other Cores
    • Integrating with the 1-Gigabit Ethernet MAC Core
      • Integration of the 1-Gigabit Ethernet MAC to 1000BASE-X PCS with TBI
      • Integration of the 1-Gigabit Ethernet MAC Using a RocketIO Transceiver
      • Integration of the 1-Gigabit Ethernet MAC to Provide SGMII (or Dynamic Switching) Functionality
    • Integrating with the Tri-Mode Ethernet MAC Core
      • Integration of the Tri-Mode Ethernet MAC to Provide SGMII (or Dynamic Switching) Functionality with TBI
      • Integration of the Tri-Mode Ethernet MAC to Provide SGMII (or Dynamic Switching) Functionality using RocketIO Transceivers
  • Special Design Considerations
    • Power Management
    • Startup Sequencing
    • Loopback
      • Core with the TBI
      • Core with RocketIO Transceiver
  • Implementing the Design
    • Pre-implementation Simulation
      • Using the Simulation Model
    • Synthesis
      • XST - VHDL
      • XST - Verilog
    • Implementation
      • Generating the Xilinx Netlist
      • Mapping the Design
      • Placing and Routing the Design
      • Static Timing Analysis
      • Generating a Bitstream
    • Post-Implementation Simulation
      • Generating a Simulation Model
      • Using the Model
    • Other Implementation Information
  • Core Verification, Compliance, and Interoperability
    • Verification
    • Simulation
    • Hardware Verification
  • Core Latency
    • Core Latency
      • Latency for 1000BASE-X PCS with TBI
      • Latency for 1000BASE-X PCS and PMA Using a RocketIO Transceiver
      • Latency for SGMII
  • Calculating the DCM Fixed Phase Shift Value
    • Requirement for DCM Phase Shifting
    • Finding the Ideal Phase Shift Value for Your System
  • 1000BASE-X State Machines
    • Introduction
    • Start of Frame Encoding
      • The Even Transmission Case
      • Reception of the Even Case
      • The Odd Transmission Case
      • Reception of the Odd Case
      • Preamble Shrinkage
    • End of Frame Encoding
      • The Even Transmission case
      • Reception of the Even Case
      • The Odd Transmission Case
      • Reception of the Odd Case
  • Rx Elastic Buffer Specifications
    • Introduction
    • Rx Elastic Buffers: Depths and Maximum Frame Sizes
      • RocketIO Rx Elastic Buffers
      • SGMII Fabric Rx Elastic Buffer
      • TBI Rx Elastic Buffer
    • Clock Correction
    • Maximum Frame Sizes for Sustained Frame Reception
    • Jumbo Frame Reception
  • Debugging Guide
    • General Checks
    • Problems with the MDIO
    • Problems with Data Reception or Transmission
    • Problems with Auto-Negotiation
    • Problems in Obtaining a Link (Auto-Negotiation Disabled)
    • Problems with a High Bit Error Rate
      • Symptoms
      • Debugging