Xilinx 1000BASE-X - Manual (Page 99)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 99
UG155 March 24, 2008
RocketIO Logic with the Fabric Rx Elastic Buffer R
RocketIO Logic with the Fabric Rx Elastic Buffer
The example design delivered with the core is split between two hierarchical layers, as
illustrated in
Figure 4-3 . The block level is designed so to be instantiated directly into
customer designs and provides the following functionality:
•
Instantiates the core from HDL
•
Connects the physical-side interface of the core to a Virtex-II Pro, Virtex-4 or Virtex-5
RocketIO transceiver via the fabric Rx Elastic Buffer
The logic implemented in the block level is illustrated in all figures throughout the
remainder of this chapter.
Virtex-II Pro Devices
The core is designed for connection to a Virtex-II Pro MGT. The connections and logic
required between the core and RocketIO transceiver are illustrated in
Figure 8-3 –the signal
names and logic in the figure precisely match those delivered with the example design
when an MGT transceiver is used.
Some modifications may be made to the MGT. For example, REFCLK may be used instead
of BREFCLK. See the Virtex-II Pro RocketIO Transceiver User Guide (UG024) for details.
Figure 8-3 shows that the Rx Elastic Buffer is implemented in the FPGA fabric between the
MGT transceiver and the core. This replaces the Rx Elastic Buffer in the MGT (which is
bypassed).
This alternative Receiver Elastic Buffer uses a single block RAM to create a buffer twice as
large as the one present in the MGT. It is able to cope with larger frame sizes before clock
tolerances accumulate and result in emptying or filling of the buffer. This is necessary to
guarantee SGMII operation at 10 Mbps, where each frame size is effectively 100 times
larger than the same frame would be at 1 Gbps because each byte is repeated 100 times (see
“Designing with Client-side GMII for the SGMII Standard,” page 59 ).
In bypassing the MGT Rx Elastic Buffer, data is clocked out of the MGT synchronously to
rxrecclk
. This must be placed on constrained local clock routing for reliable operation.
See “Virtex-II Pro RocketIO MGTs for SGMII or Dynamic Standards Switching
Constraints,” page 163 for constraint details. This methodology is also described in
XAPP763.
Note: The brefclk differential pair applied to the MGT is of frequency 62.5 MHz.