Xilinx 1000BASE-X - Manual (Page 137)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 137
UG155 March 24, 2008
Management Registers R
Register 1: SGMII Status
0.5 Unidirectiona
l Enable Enable transmit regardless of
whether a valid link has been
established read/ write 0
0.4:0 Reserved Always return 0s , writes ignored returns 0s 00000
Table 9-19: SGMII Control (Register 0) (Continued)
Bit(s) Name Description Attributes
Default
Value
MDIO Register 1: SGMII Status
Table 9-20: SGMII Status (Register 1)
Bit(s) Name Description Attributes
Default
Value
1.15 100BASE-T4 Always returns a ‘0’ for this bit because
100BASE-T4 is not supported returns 0 0
1.14 100BASE-X Full
Duplex Always returns a ‘0’ for this bit because
100BASE-X Full Duplex is not supported returns 0 0
1.13 100BASE-X Half
Duplex Always returns a ‘0’ for this bit because
100BASE-X Half Duplex is not supported returns 0 0
1.12 10 Mbps Full Duplex Always returns a ‘0’ for this bit because 10
Mbps Full Duplex is not supported returns 0 0
1.11 10 Mbps Half Duplex Always returns a ‘0’ for this bit because 10
Mbps Half Duplex is not supported returns 0 0
1.10 100BASE-T2 Full
Duplex Always returns a ‘0’ for this bit because
100BASE-T2 Full Duplex is not supported returns 0 0
1.9 100BASE-T2 Half
Duplex Always returns a ‘0’ for this bit because
100BASE-T2 Half Duplex is not
supported returns 0 0
1.8 Extended Status Always returns a ‘1’ for this bit to indicate
the presence of the Extended Register
(Register 15) returns 1 1
100BASE-T4 100BASE-X FULL DUPLEX 10Mb/s FULL DUPLEX 100BASE-T2 HALF DUPLEX LINK ST
A
TUS
10Mb/s HALF DUPLEX 100BASE-X HALF DUPLEX MF PREAMBLE SUPPRESSION
15 14 13 12 11 10 7 6 5 0
Reg 1
100BASE-T2 FULL DUPLEX
9 8
EXTENDED ST
A
T
US
UNIDIRECTIONAL ANILITY
4
A
U
T
O-NEG COMPLETE
3 2 1
REMO
TE F
A
UL
T
A
U
T
O-NEG ABILITY
J
ABBER DETECT
EXTENDED CAP
ABILITY