Xilinx 1000BASE-X - Manual (Page 186)

186 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 13: Interfacing to Other Cores R
•
If both cores have been generated with the optional management interface, the MDIO
port can be connected to that of the Tri-Speed Ethernet MAC core, allowing the MAC
to access the embedded configuration and status registers of the Ethernet 1000BASE-X
PCS/PMA or SGMII core.
•
Due to the Receiver Elastic Buffer in the core, the entire GMII (transmitter and receiver
paths) is synchronous to a single clock domain. Therefore, the txcoreclk and
rxcoreclk
inputs of the Tri-Speed Ethernet MAC core can always be driven from
the same clock source.
Figure 13-7 illustrates the Tri-Mode Ethernet MAC core generated with the optional clock
enable circuitry. This is the most efficient way to connect the two cores together in terms of
clock resource usage and so is recommended. See the Tri-Mode Ethernet MAC User Guide for
more information.