Table 9-3, Register 0: control register – Xilinx 1000BASE-X User Manual
Page 120
120
Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 9: Configuration and Status
R
Register 0: Control Register
2,3
PHY Identifier
4
Auto-Negotiation Advertisement Register
5
Auto-Negotiation Link Partner Ability Base Register
6
Auto-Negotiation Expansion Register
7
Auto-Negotiation Next Page Transmit Register
8
Auto-Negotiation Next Page Receive Register
15
Extended Status Register
16
Vendor Specific: Auto-Negotiation Interrupt Control
Table 9-2:
MDIO Registers for 1000BASE-X with Auto-Negotiation (Continued)
Register Address
Register Name
MDIO Register 0: Control Register
Table 9-3:
Control Register (Register 0)
Bit(s)
Name
Description
Attributes
Default
Value
0.15
Reset
1 = Core Reset
0 = Normal Operation
Read/write
Self clearing
0
0.14
Loopback
1 = Enable Loopback Mode
0 = Disable Loopback Mode
When used with a RocketIO
transceiver, the core is placed in
internal loopback mode.
With the TBI version, Bit 1 is
connected to ewrap. When set to ‘1,’
indicates to the external PMA
module to enter loopback mode.
See
Read/write
0
RESET
LOOPBA
CK
A
U
T
O-NEG ENABLE
REST
AR
T A
U
T
O-NEG
RESER
VED
PO
WER DO
WN
SPEED
SPEED
15 14 13 12 11 10
7
6
5
0
Reg 0
ISOLA
TE
9
8
DUPLEX MODE
COLLISION TEST
4
UNIDIRECTIONAL ENABLE