Xilinx 1000BASE-X - Manual (Page 26)

26 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1
UG155 March 24, 2008
Chapter 2: Core Architecture R
8B/10B Encoder
8B10B encoding, as defined in IEEE 802.3 (Tables 36-1a to 36-1e and Table 36-2), is
implemented in a block SelectRAM™, configured as ROM, and used as a large look-up
table.
8B/10B Decoder
8B10B decoding, as defined in IEEE 802.3 (Table 36-1a to 36-1e and Table 36-2), is
implemented in a block SelectRAM, configured as ROM, and used as a large look-up table.
Receiver Elastic Buffer
The Receiver Elastic Buffer enables the 10-bit parallel TBI data, received from the PMA
sublayer synchronously to the TBI receiver clocks, to be transferred onto the cores internal
125 MHz clock domain. It is an asynchronous FIFO implemented in internal RAM. The
Receiver Elastic Buffer attempts to maintain a constant occupancy by inserting or
removing Idle sequences as necessary. This causes no corruption to the frames of data.
TBI Block
The core provides a TBI interface that should be routed to device IOBs to provide an off-
chip TBI.
Core Interfaces
All ports of the core are internal connections in FPGA fabric. An HDL example design
(delivered with the core) connects the core, where appropriate, to a RocketIO transceiver,
and/or add IBUFs, OBUFs, and IOB flip-flops to the external signals of the GMII and TBI.
IOBs are added to the remaining unconnected ports to take the example design through
the Xilinx implementation software.
All clock management logic is placed in this example design, allowing you more flexibility
in implementation (such as designs using multiple cores). This example design is provided
in both VHDL and Verilog. For more information, see the Ethernet 1000BASE-X PCS/PMA
or SGMII Getting Started Guide.
Figure 2-3 shows the pinout for the Ethernet 1000BASE-X PCS/PMA or SGMII core using
a RocketIO transceiver with the optional PCS Management Registers. The signals shown in
the Auto-Negotiation box included only when the core includes the Auto-Negotiation