Xilinx LOGICORE UG144 User Manual
Logicore™ ip 1-gigabit ethernet mac v8.5, User guide
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Table of contents
Document Outline
- LogiCORE™ IP 1-Gigabit Ethernet MAC v8.5
- About This Guide
- Introduction
- Core Architecture
- Generating the Core
- Designing with the Core
- Using the Client Side Data Path
- Using Flow Control
- Using the Physical Side Interface
- Configuration and Status
- Constraining the Core
- Required Constraints
- Device, Package, and Speedgrade Selection
- I/O Location Constraints
- Placement Constraints
- Timing Constraints
- Constraints when Implementing an External GMII
- Understanding Timing Reports for GMII Setup/Hold Timing
- Constraints when Implementing an External RGMII
- Understanding Timing Reports for RGMII Setup/Hold timing
- Required Constraints
- Clocking and Resetting
- Interfacing to Other Cores
- Implementing Your Design
- Using the Client-Side FIFO
- Core Verification, Compliance, and Interoperability
- Calculating DCM Phase-Shifting
- Core Latency