Xilinx LOGICORE UG144 - Manual (Page 29)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 29
UG144 April 24, 2009
Core Interfaces R
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Configuration Vector (Optional)
Table 2-6 describes the alternative to the optional Management Interface signals. The
Configuration Vector uses direct inputs to the core to replace the functionality of the MAC
configuration bits. See
“Access without the Management Interface,” on page 90 .
Asynchronous Reset
Table 2-7 describes the asynchronous reset signal for the entire core.
Physical Side Interface
GMII
Table 2-8 describes the GMII-style interface signals of the core. See Chapter 7, “Using the
Physical Side Interface.”
Table 2-6: Optional Configuration Vector Signal Pinout
Signal Direction Description
configuration_vector[67:0] Input Used to replace the functionality of
the MAC Configuration Registers
when the Management Interface is
not used
Note: All bits are registered on input but may be treated as asynchronous inputs.
Table 2-7: Reset Signal
Signal Direction Clock Domain Description
reset Input n/a Asynchronous reset for entire core
Table 2-8: GMII Interface Signal Pinout
Signal Direction Clock Domain Description
gmii_txd[7:0] Output gtx_clk Transmit data from MAC
gmii_tx_en Output gtx_clk Transmit control signal from MAC
gmii_tx_er Output gtx_clk Transmit control signal from MAC
gmii_rx_clk Input n/a Receive clock from external PHY (125
MHz)
gmii_rxd[7:0] Input gmii_rx_clk Received data to MAC
gmii_rx_dv Input gmii_rx_clk Received control signal to MAC
gmii_rx_er Input gmii_rx_clk Received control signal to MAC