Xilinx LOGICORE UG144 - Manual (Page 117)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 117
UG144 April 24, 2009
Ethernet 1000Base-X PCS/PMA or SGMII Core R
-- DISCONTINUED PRODUCT --
Virtex-5 LXT and SXT Devices
Figure 11-3 illustrates the connections and clock management logic required to interface
the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in
1000BASE-X mode with PMA using the device-specific RocketIO transceiver).
Figure 11-3 illustrates the following:
• Direct internal connections are made between the GMII interfaces between the two
cores.
•
If the GEMAC has been generated with the optional Management Interface, the
MDIO port can be connected to that of the Ethernet 1000BASE-X PCS/PMA or SGMII
core to access its embedded configuration and status registers. See
“Using the
Optional Management Interface.”
Figure 11-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA
using a RocketIO transceiver
1-Gigabit Ethernet
MAC
LogiCORE
gmii_rx_clk
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
gtx_clk
mdc
mdio_in
mdio_out
mdio_tri
Ethernet 1000BASE-X
PCS/PMA or SGMII
LogiCORE
gmii_rxd[7:0]
gmii_rx_dv
gmii_rx_er
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
mdc
mdio_in
mdio_out
mdio_tri
Virtex-5
GTP
RocketIO
no
connection
userclk
userclk2
RocketIO I/F
CLKIN
userclk2
(125 MHz)
TXUSRCLK0
TXUSRCLK20
RXUSRCLK0
RXUSRCLK20
BUFG
TXOUTCLK0
component_name_block
(Block Level from example design)
clkin
(125MHz)
IBUFGDS
IPAD
brefclkp
IPAD
brefclkn