Xilinx LOGICORE UG144 - Manual (Page 25)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 25
UG144 April 24, 2009
Core Interfaces R
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GEMAC Core Without Management Interface and Without Address Filter
Figure 2-4 shows the pinout for the GEMAC core when the optional Management Interface
is omitted and the optional Address Filter is omitted.
The configuration_vector[67:0] input provides the method for configuration of
the core.
Figure 2-4: Component Pinout for MAC without Optional Management Interface or Optional Address Filter
gmii_rx_clk
gmii_rxd[7:0]
gmii_txd[7:0]
gmii_tx_en
gmii_tx_er
reset
gmii_rx_dv
gmii_rx_er
gtx_clk domain
gmii_rx_clk domain
Client Side Interface Physical Side Interface (GMII)
configuration_vector[67:0]
gtx_clk
tx_data[7:0]
tx_ack
tx_underrun
pause_req
pause_val[15:0]
tx_data_valid
tx_ifg_delay[7:0]
tx_statistics_vector[31:0]
tx_statistics_valid
rx_data[7:0]
rx_good_frame
rx_bad_frame
rx_data_valid
rx_statistics_vector[27:0]
rx_statistics_valid