Xilinx LOGICORE UG144 - Manual (Page 10)

10 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
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Chapter 7: Using the Physical Side Interface
Figure 7-1: External GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 7-2: External GMII Receiver Logic for Spartan-3, Spartan-3E, and
Spartan-3A Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 7-3: External GMII Receiver Logic for Virtex-5 Devices . . . . . . . . . . . . . . . . . . . . . 65
Figure 7-4: External RGMII Transmitter Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 7-5: External RGMII Transmitter Logic in Virtex-4 Devices. . . . . . . . . . . . . . . . . . 68
Figure 7-6: External RGMII Transmitter Logic in Virtex-5 Devices. . . . . . . . . . . . . . . . . . 69
Figure 7-7: External RGMII Receiver Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 7-8: External RGMII Receiver Logic for Virtex-4 Devices . . . . . . . . . . . . . . . . . . . . 73
Figure 7-9: External RGMII Receiver Logic for Virtex-5 Devices . . . . . . . . . . . . . . . . . . . . 74
Figure 7-10: RGMII Inband Status Decoding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 7-11: Creating an External MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Chapter 8: Configuration and Status
Figure 8-1: Configuration Register Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 8-2: Configuration Register Read Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 8-3: Address Table Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 8-4: Address Table Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 8-5: Typical MDIO-managed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 8-6: MDIO Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 8-7: MDIO Read Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 8-8: MDIO Access through Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 9: Constraining the Core
Figure 9-1: Input GMII Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 9-2: Timing Report Setup/Hold Illustration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 9-3: Input RGMII Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 9-4: Timing Report Setup/Hold Illustration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Chapter 10: Clocking and Resetting
Figure 10-1: Clock Management Logic with External GMII . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 10-2: Clock Management with External RGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 10-3: Clock Management Logic with External GMII (Multiple Cores). . . . . . . . 111
Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores) . . . . . . 112
Figure 10-5: Reset Circuit for a Single Clock/reset Domain. . . . . . . . . . . . . . . . . . . . . . . . 112