Document Outline

• LogiCORE™ IP 1-Gigabit Ethernet MAC v8.5
  • About This Guide
    • Guide Contents
    • Conventions
      • Typographical
      • Online Document
      • List of Acronyms
  • Introduction
    • About the Core
    • Recommended Design Experience
    • Additional Core Resources
    • Related Xilinx Ethernet Products and Services
    • Specifications
    • Technical Support
    • Feedback
      • GEMAC Core
      • Document
  • Core Architecture
    • System Overview
      • Core Components
    • Core Interfaces
      • GMAC Core with Optional Management Interface
      • GMAC Core Without Management Interface and With Address Filter
      • GEMAC Core Without Management Interface and Without Address Filter
      • Client Side Interface
      • Physical Side Interface
  • Generating the Core
    • Graphical User Interface
      • Component Name
      • Management Interface
      • Address Filter
      • Number of Address Table Entries
      • Physical Interface
    • Parameter Values in the XCO File
    • Output Generation
  • Designing with the Core
    • General Design Guidelines
      • Design Steps
      • Know the Degree of Difficulty
      • Keep it Registered
      • Recognize Timing Critical Signals
      • Use Supported Design Flows
      • Make Only Allowed Modifications
  • Using the Client Side Data Path
    • Receiving Inbound Frames
      • Normal Frame Reception
      • rx_good_frame, rx_bad_frame timing
      • Frame Reception with Errors
      • Client-Supplied FCS Passing
      • VLAN Tagged Frames
      • Maximum Permitted Frame Length
      • Length/Type Field Error Checks
      • Address Filter
      • Receiver Statistics Vector
    • Transmitting Outbound Frames
      • Normal Frame Transmission
      • Padding
      • Client-Supplied FCS Passing
      • Client Underrun
      • VLAN Tagged Frames
      • Maximum Permitted Frame Length
      • Inter-Frame Gap Adjustment
      • Transmitter Statistics Vector
  • Using Flow Control
    • Overview of Flow Control
      • Flow Control Requirement
      • Flow Control Basics
      • Pause Control Frames
    • Flow Control Operation of the GEMAC
      • Transmitting a PAUSE Control Frame
      • Receiving a Pause Control Frame
    • Flow Control Implementation Example
  • Using the Physical Side Interface
    • Implementing External GMII
      • GMII Transmitter Logic
      • GMII Receiver Logic
    • Implementing External RGMII
      • RGMII Transmitter Logic
      • RGMII Receiver Logic
      • RGMII Inband Status Decoding Logic
    • Using the MDIO interface
      • Connecting the MDIO to an Internally Integrated PHY
      • Connecting the MDIO to an External PHY
  • Configuration and Status
    • Using the Optional Management Interface
      • Host Clock Frequency
      • Configuration Registers
      • MDIO Interface
    • Access without the Management Interface
  • Constraining the Core
    • Required Constraints
      • Device, Package, and Speedgrade Selection
      • I/O Location Constraints
      • Placement Constraints
      • Timing Constraints
      • Constraints when Implementing an External GMII
      • Understanding Timing Reports for GMII Setup/Hold Timing
      • Constraints when Implementing an External RGMII
      • Understanding Timing Reports for RGMII Setup/Hold timing
  • Clocking and Resetting
    • Clocking the Core
      • With Internal GMII
      • With External GMII
      • With RGMII
    • Multiple Cores
      • With External GMII
      • With RGMII
    • Reset Conditions
  • Interfacing to Other Cores
    • Ethernet 1000Base-X PCS/PMA or SGMII Core
      • Integration to Provide 1000BASE-X PCS with TBI
      • Integration to Provide 1000BASE-X PCS and PMA using a RocketIO Transceiver
      • Integration to Provide SGMII Functionality
    • Ethernet Statistics Core
      • Connecting the Ethernet Statistics Core to Provide Statistics Gathering
  • Implementing Your Design
    • Pre-implementation Simulation
      • Using the Simulation Model
    • Synthesis
      • XST-VHDL
      • XST-Verilog
    • Implementation
      • Generating the Xilinx Netlist
      • Mapping the Design
      • Placing-and-Routing the Design
      • Static Timing Analysis
      • Generating a Bitstream
    • Post-Implementation Simulation
      • Generating a Simulation Model
      • Using the Model
    • Other Implementation Information
  • Using the Client-Side FIFO
    • Interfaces
      • Transmit FIFO
      • Receive FIFO
    • Overview of LocalLink Interface
      • Data Flow
    • Functional Operation
      • Clock Requirements
      • Receive FIFO
      • Transmit FIFO
      • Expanding Maximum Frame Size
      • User Interface Data Width Conversion
  • Core Verification, Compliance, and Interoperability
    • Verification by Simulation
    • Hardware Verification
  • Calculating DCM Phase-Shifting
    • DCM Phase-Shifting
    • Finding the Ideal Phase-Shift
  • Core Latency
    • Transmit Path Latency
    • Receive Path Latency