Xilinx LOGICORE UG144 - Manual (Page 96)

96 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 9: Constraining the Core R
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Timespecs for Reset Logic within the Core
Internally, the core is divided into clock/reset domains that group elements with common
clock and reset signals. The reset circuitry for one of these domains is illustrated in
Figure 10-5 . This circuit provides controllable skews on the reset nets within the design.
The following UCF syntax identifies the relevant reset logic and groups them together.
Timing constraints are then applied to constrain the skews on the reset nets:
INST "*gmac_core/BU2/U0/SYNC_RX_RESET_I/RESET_OUT" TNM = "reset_dist_grp";
INST "*gmac_core/BU2/U0/SYNC_TX_RESET_I/RESET_OUT" TNM = "reset_dist_grp";
INST "*gmac_core/BU2/U0/G_SYNC_MGMT_RESET?SYNC_MGMT_RESET_HOST_I/RESET_OUT" TNM =
"reset_dist_grp";
TIMESPEC "TS_reset_dist" = FROM "reset_dist_grp" 6100 ps;
Note: The third line in the preceding UCF syntax is only required when the optional Management
Interface is used.
Constraints when Implementing an External GMII
The constraints defined in this section are implemented in the UCF for the example design
delivered with the core. Sections from this UCF are copied into the following descriptions
to provide examples. These examples should be studied in conjunction with the HDL
source code for the example design and with the description
“Implementing External
GMII,” on page 61 .
GMII IOB Constraints
The following constraints target the flip-flops that are inferred in the top-level HDL file for
the example design; constraints are set to ensure that these are placed in IOBs.
# GMII Transmitter Constraints: place flip-flops in IOB
INST "*gmii_interface/gmii_txd_reg*" IOB = true;
INST "*gmii_interface/gmii_tx_en_reg" IOB = true;
INST "*gmii_interface/gmii_tx_er_reg" IOB = true;
# GMII Receiver Constraints: place flip-flops in IOB
INST "*gmii_interface/gmii_rxd_reg*" IOB = true;
INST "*gmii_interface/gmii_rx_dv_reg" IOB = true;
INST "*gmii_interface/gmii_rx_er_reg" IOB = true;
The GMII is a 3.3 volt signal-level interface which is not the default SelectIO™ standard.
Therefore, use the following constraints with the device IO Banking rules.
INST "gmii_txd<?>" IOSTANDARD = LVTTL;
INST "gmii_tx_en" IOSTANDARD = LVTTL;
INST "gmii_tx_er" IOSTANDARD = LVTTL;
INST "gmii_rxd<?>" IOSTANDARD = LVTTL;
INST "gmii_rx_dv" IOSTANDARD = LVTTL;
INST "gmii_rx_er" IOSTANDARD = LVTTL;
INST "gmii_tx_clk" IOSTANDARD = LVTTL;
INST "gmii_rx_clk" IOSTANDARD = LVTTL;
In addition, the example design provides pad locking on the GMII for several families.
This is a provided as a guideline only; there are no specific I/O location constraints for this
core.