Xilinx LOGICORE UG144 - Manual (Page 66)

66 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 7: Using the Physical Side Interface R
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Implementing External RGMII
The HDL example design delivered with the core implements an external RGMII when
RGMII is selected from the CORE Generator GUI (see
Chapter 3, “Generating the Core” ).
For more information about using the example design, see the 1-Gigabit Ethernet MAC
Getting Started Guide.
RGMII Transmitter Logic
Spartan-3, Spartan-3E, Spartan-3A and Spartan-3A DSP Devices
Figure 7-4 illustrates how to use the physical transmitter interface of the core to create an
external RGMII in a Spartan-3 device. The signal names and logic precisely match those
delivered with the example design when the RGMII is selected. If other families are used,
equivalent primitives and logic specific to that family is used in the example design.
Figure 7-4: External RGMII Transmitter Logic
IPAD
IBUFG
IOB LOGIC
gtx_clk
BUFG
gtx_clk_bufg
rgmii_txc
IOB LOGIC
OBUF
FDDRRSE
OPAD
D Q
D Q
'1'
'0'
1-Gigabit Ethernet MAC Core
gmii_txd_int[0]
gmii_tx_en_int
gmii_tx_er_int
gtx_clk gmii_txd[0]
gmii_tx_en
gmii_tx_er
DCM
CLKIN
CLK0 FB
CLK90
IOB LOGIC
D Q
OBUF
FDDRRSE
OPAD
D Q
D Q D Q
D Q
D Q
OBUF
FDDRRSE
OPAD
D Q
D Q D Q
D Q
gmii_txd[4]
gmii_txd_int[4]
rgmii_txd[0]
rgmii_tx_ctl
rgmii_tx_clk_bufg