Xilinx LOGICORE UG144 - Manual (Page 84)

84 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 8: Configuration and Status R
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Reading from the configuration register words is similar, but the upper host_opcode bit
should be ‘1,’ as shown in
Figure 8-2 . In this case, the contents of the register appear on
host_rd_data the host_clk edge after the register address is asserted onto
host_addr .
Figure 8-1: Configuration Register Write Timing
Figure 8-2: Configuration Register Read Timing
host_clk
host_addr[8:0]
host_addr[9]
host_opcode[1]
host_miim_sel
host_wr_data[31:0]
host_clk
host_addr[8:0]
host_addr[9]
host_opcode[1]
host_miim_sel
host_rd_data[31:0]