Xilinx LOGICORE UG144 - Manual (Page 121)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 121
UG144 April 24, 2009
Ethernet Statistics Core R
-- DISCONTINUED PRODUCT --
The management interfaces of the two cores can be shared by avoiding bus conflict, as
follows:
• Selecting a different address range for the statistics to that of the MAC configuration
registers. This is achieved by setting host_addr[9] to logic 0 when reading from the
statistics and logic 1 when writing and reading to the MAC configuration registers.
• Using the host_miim_sel signal to differentiate between a statistical counter read
and a MAC initiated MDIO transaction. This is achieved by setting host_miim_sel
to logic 0 for a statistical counter read and logic 1 for a MAC initiated MDIO
transaction.
Table 11-1 describes the type of host transactions that occur if the host interface is shared
(as illustrated in Figure 11-5 ).
Table 11-1: Management Interface Transaction Types
Transaction host_miim_sel host_addr[9]
Configuration 0 1
MIIM access 1 X
Statistics Read 0 0