Xilinx LOGICORE UG144 - Manual (Page 112)

112 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Chapter 10: Clocking and Resetting R
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Reset Conditions
Internally, the core is divided up into clock/reset domains that group together elements
with common clock and reset signals. The reset circuitry for one of these domains is
illustrated in
Figure 10-5 . This circuit provides controllable skews on the reset nets within
the design.
Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores)
IBUFG
BUFG
gtx_clk
rgmii_rxc1
gmii_rx_clk
gmii_rx_clk
gtx_clk
gtx_clk
IBUFG
BUFG
CLK_0
CLK_90
DCM
CLK_0
DCM
RGMII Tx Logic RGMII Rx Logic
1-Gigabit Ethernet MAC Core
1-Gigabit Ethernet MAC Core
RGMII Tx Logic
IBUFG
BUFG
rgmii_rxc2
CLK_0
DCM
RGMII Rx Logic
BUFG
Figure 10-5: Reset Circuit for a Single Clock/reset Domain
FDP
PRE
D
C
Q
FDP
PRE
D
C
Q
FDP
PRE
D
C
Q
FDP
PRE
D
C
Q
PRE PRE PRE
'0'
reset
Configuration reset
Clock
Core Registers