Xilinx LOGICORE UG144 - Manual (Page 105)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 105
UG144 April 24, 2009
Required Constraints R
-- DISCONTINUED PRODUCT --
Understanding Timing Reports for RGMII Setup/Hold timing
Non-Virtex-5 Devices
Setup and Hold results for the RGMII input bus can be found in the data sheet section of
the Timing Report. The results are self-explanatory and it is easy to see how they relate to
Figure 9-3 .
Following is an example for the RGMII report from a Virtex-4 device. Each Input lists two
sets of values—one corresponding to the –ve edge of the clock and one to the +ve edge. The
first set listed corresponds to –ve edge which occurs at time 4 ns. The implementation
requires 0.648 ns of setup to the –ve edge and 0.661 ns to the +ve edge. This is less than the
1 ns required, so there is slack. The implementation requires 0.300 ns of hold to the –ve
edge and 0.316 ns to the +ve edge. This is less than the 1 ns required, so there is slack.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock rgmii_rxc
------------+------------+------------+---------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+---------------------+--------+
rgmii_rx_ctl| -3.352(R)| 4.300(R)|not_rgmii_rx_clk_bufg| 4.938|
| 0.661(R)| 0.284(R)|rgmii_rx_clk_bufg | 0.938|
rgmii_rxd<0>| -3.384(R)| 4.332(R)|not_rgmii_rx_clk_bufg| 4.938|
| 0.629(R)| 0.316(R)|rgmii_rx_clk_bufg | 0.938|
rgmii_rxd<1>| -3.348(R)| 4.296(R)|not_rgmii_rx_clk_bufg| 4.938|
| 0.665(R)| 0.280(R)|rgmii_rx_clk_bufg | 0.938|
rgmii_rxd<2>| -3.360(R)| 4.308(R)|not_rgmii_rx_clk_bufg| 4.938|
| 0.653(R)| 0.292(R)|rgmii_rx_clk_bufg | 0.938|
rgmii_rxd<3>| -3.428(R)| 4.382(R)|not_rgmii_rx_clk_bufg| 4.938|
| 0.585(R)| 0.366(R)|rgmii_rx_clk_bufg | 0.938|
------------+------------+------------+---------------------+--------+
Virtex-5 devices with delayed Data/Control
Setup and Hold results for the RGMII input bus can be found in the data sheet section of
the Timing Report. The results are self-explanatory and it is easy to see how they relate to
Figure 9-3 .
Following is an example for the RGMII report from a Virtex-5 device. Each Input lists two
sets of values—one corresponding to the –ve edge of the clock and one to the +ve edge. The
first set listed corresponds to +ve edge which occurs at time 0 ns. The implementation
requires 0.818 ns of setup to the +ve edge and 0.794 ns to the –ve edge. This is less than the
1 ns required, so there is slack. The implementation requires 0.946 ns of hold to the –ve
edge and 0.972 ns to the +ve edge. This is less than the 1 ns required, so there is slack.