Xilinx LOGICORE UG144 - Manual (Page 91)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 91
UG144 April 24, 2009
Access without the Management Interface R
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53 “Receiver
Configuration
Word 1”
bit 31
n/a Receiver Reset . When this bit is ‘1,’ the
receiver is held in reset. This signal is an input
to the reset circuit for the receiver block.
54 “Transmitter
Configuration
Word”
bit 25
gtx_clk Transmitter Interframe Gap Adjust Enable
If ‘1,’ then the transmitter will read the value
of the tx_ifg_delay port and set the interframe
gap accordingly. If ‘0,’ the transmitter will
always insert at least the legal minimum
interframe gap.
55 n/a n/a This input is unused.
56 “Transmitter
Configuration
Word”
bit 27
gtx_clk Transmitter VLAN Enable When this bit is
set to ‘1,’ the transmitter allows the
transmission of VLAN tagged frames.
57 “Transmitter
Configuration
Word”
bit 28
gtx_clk Transmitter Enable When this bit is ‘1,’ the
transmitter will be operational. When it is ‘0,’
the transmitter is disabled.
58 “Transmitter
Configuration
Word”
bit 29
gtx_clk Transmitter In-Band FCS Enable When this
bit is ‘1,’ the MAC transmitter will expect the
FCS field to be pass in by the client. When it
is ‘0,’ the MAC transmitter will append
padding as required, compute the FCS and
append it to the frame.
59 “Transmitter
Configuration
Word”
bit 30
gtx_clk Transmitter Jumbo Frame Enable When this
bit is ‘1,’ the MAC transmitter will allow
frames larger than the maximum legal frame
length specified in IEEE 802.3-2005 to be sent.
When set to ‘0,’ the MAC transmitter will
only allow frames up to the legal maximum
to be sent.
60 “Transmitter
Configuration
Word”
bit 31
n/a Transmitter Reset . When this bit is ‘1,’ the
MAC transmitter is held in reset. This signal
is an input to the reset circuit for the
transmitter block.
61 “Flow Control
Configuration
Word”
bit 29
gtx_clk Transmit Flow Control Enable . When this
bit is ‘1,’ asserting the pause_req signal
causes the GEMAC core to send a flow
control frame out from the transmitter. When
this bit is ‘0,’ asserting the pause_req signal
will have no effect.
Table 8-13: Configuration Vector Bit Definition (Continued)
Bit(s)
Configuration
Register cross
reference
Clock Description