Xilinx LOGICORE UG144 - Manual (Page 21)

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 21
UG144 April 24, 2009
R
-- DISCONTINUED PRODUCT --
Chapter 2
Core Architecture
This chapter describes the GEMAC core architecture, including the major functional blocks
and all interfaces.
System Overview
Figure 2-1 illustrates a block diagram of the GEMAC core with all the major functional
blocks and interfaces. Descriptions of the functional blocks and interfaces are provided in
the sections that follow.
Figure 2-1: Block Diagram
Gigabit Ethernet MAC Core
Flow Control
Transmit Engine
Receive Engine
Configuration MDIO
Optional
Address
Filter
Client
Transmitter
Interface
Client
Management
Interface
Client
Receiver
Interface
To Physical
Sublayers
Client Interf
a
ce
GMII Bloc
k
Optional Management