Expanding maximum frame size, User interface data width conversion – Xilinx LOGICORE UG144 User Manual
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1-Gigabit Ethernet MAC v8.5 User Guide
UG144 April 24, 2009
Appendix A: Using the Client-Side FIFO
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Verilog
The compiler directive FULL_DUPLEX_ONLY is defined to allow for removal of logic and
performance constraints that are necessary only in half-duplex operation, that is, when
using with the Tri-Mode Ethernet MAC core. This directive can always be defined when
the FIFO is used with the GEMAC.
The FIFO has two signal inputs specific to half-duplex operation, tx_collision and
tx_retransmit
. These signals are provided to make the FIFO compatible with both the
1-Gigabit Ethernet MAC and Tri-Mode Ethernet MAC cores, and should be tied to logic 0
when using the FIFO with the GEMAC core.
If the FIFO memory fills up, the dst_rdy_out_n signal is used to halt the LocalLink
interface writing in data until space becomes available in the FIFO. If the FIFO memory
fills up but no frames are available for transmission (for example, if a frame larger than
4000 bytes is written into the FIFO), the FIFO may assert the tx_overflow signal and
continue to accept the rest of the frame from the user. The overflow frame will be dropped
by the FIFO. This ensures that the LocalLink interface does not lock up. For this reason, it
is recommended that the FIFO not be used with the GEMAC in jumbo frame mode for
frames larger than 4000 bytes.
Expanding Maximum Frame Size
The transmit FIFO size is optimized to allow line rate transmission of maximum size
Ethernet frames at 1518 bytes in half-duplex operation.
When using the FIFO in full-duplex operation, the full block RAM capacity can be utilized
at all times. As a whole frame must be stored in the FIFO block RAM before being
presented to the MAC transmitter, the maximum size frame that can be handled is
determined by the memory capacity of the FIFO (in this case 4000 bytes).
Both transmit and receive FIFO sizes can be expanded by the user to handle larger frame
sizes. This can be done by instantiating further block RAMs into the FIFO design,
expanding the block RAM address signals, and adding the necessary control signals. The
HDL source files provide guidance in the comments on how to achieve this.
User Interface Data Width Conversion
Conversion of the user interface 8 bit data path to a 16, 32, 64 or 128 bit data path can be
made by connecting the LocalLink interface directly to the Parameterizable LocalLink
FIFO, Xilinx Application Note
Parameterizable LocalLink FIFO
found at
.